White paper
Over 10× reduction in logical error rates with Meridian
Purpose-built AI for fault-tolerant quantum computing
The first fault-tolerant quantum computer will be designed with AI. That’s because a quantum computer's architecture determines how long the machine takes to build, and a good architecture can save years of development and several million dollars in capital expenditure. The advantage, therefore, goes to whoever can explore the design space more smartly and figure out which candidates are worth building. Today, that work depends on a small number of people with the breadth of expertise to do it.
Meridian is QC Design's purpose-built AI system for fault-tolerant quantum computing. It combines AI-driven design exploration with hardware-specific modelling and validation through Plaquette, our quantum design-automation software.
Meridian expands what architecture teams can explore.
Its specialized AI scientists draw on frontier models, human-curated knowledge bases and the validation and simulation tools of Plaquette, our quantum design-automation software. Plaquette provides an accurate world-model, allowing Meridian to test and validate candidates under realistic hardware imperfections and use the results to find architectures that hold up to the reality of hardware.
We test Meridian on one crucial layer of the stack: designing circuits that act on physical qubits to implement a given error-correction code on a device whose hardware layout and error model are specified. We run this test on an eval suite comprising over 100 tasks that span 10 code families and six connectivity classes, with error models representing all major hardware platforms. We compare Meridian with the best methods from published literature and a baseline agent running GPT-6 Astra with internet access and open-source FTQC design tools. Plaquette is used to evaluate Meridian’s submitted circuits under each task’s specified error model. The baseline agent’s circuits are also evaluated separately from the agent’s own performance estimates.
Across all the tasks, Meridian achieved a lower evaluated logical error rate than the best methods in published literature. Meridian’s median improvement versus literature was 14.6× with improvements ranging from 1.5× to over 22,000×. This means that for the median tasks, the same hardware could be used to run a 14.6× deeper circuit as compared to the best reported methods in literature.
Against the baseline agent, Meridian achieved a median reduction in logical error rate of approximately 43%, corresponding to an improvement factor of 1.77×, with improvements reaching approximately 63×. The 14.6× result is a comparison between Meridian with published methods and the 1.77× result with the baseline agent.
In one of many striking examples, Meridian reduced logical errors by 29-fold relative to the reference circuit generated from published methods and by 40% relative to the baseline agent under the task's silicon-spin noise model.
These results provide early evidence that a purpose-built AI system can use an accurate world model and knowledge of quantum error correction to develop better designs. The next step is for Meridian to evaluate architecture choices across the full stack, measuring their effect on the physical qubits and runtime required for a logical computation.
Our aim is to give every hardware team the capacity to explore architectures it could not otherwise design, to understand why they work and to reach fault tolerance years sooner.
About the white paper
How are the designs tailored to different quantum hardware?
Each task corresponds to the design of a syndrome extraction circuit of an error-correction code for a given hardware. The inputs to the task include a description of the code, the hardware’s available connections and native gates, and an error model describing imperfections resulting from the action of gates, measurements and idle periods.
For example, in a silicon-spin task, Meridian used available helper qubits to remove leakage between error-correction rounds, alongside shorter gate schedules and changes of basis during idle periods to reduce the effects of dephasing.
The evaluation suite includes tasks from across 10 code families and error models representing the major hardware platforms of neutral atoms, trapped ions, solid-state spins, superconducting and photonic qubits. The code and hardware layout are fixed within each task, so the results measure improvements from circuit design under the specified hardware conditions.
What do the two benchmark comparisons tell us?
Against published methods, Meridian achieved a median improvement of 14.6× in logical error rate. For each task, the reference was the best-performing circuit from two sources: published construction methods, adapted to the hardware with the best available transpilers, and hand-crafted device-specific circuits from the literature.
Against a baseline agent running GPT-6 Astra at maximum reasoning effort, with internet access and open-source fault-tolerant quantum computing tools, Meridian achieved a median improvement of 1.77×, corresponding to approximately 43% lower logical error rates.
Both figures describe logical error rates evaluated in simulation for memory circuits, with the error-correction code, hardware layout and error model fixed for each task.
How were the results validated?
Meridian’s circuits and the baseline agent’s circuits were evaluated in Plaquette under the same predefined error model for each task, separately from the baseline agent’s own performance estimates.
We also cross-checked all 136 circuits from the 34 tasks containing only Pauli noise using the public release of Stim, rebuilding the noise directly from the task specifications with no Plaquette code in the noise or sampling path. All 136 agreed with the white paper’s reported logical error rates at 95% confidence.
Since Plaquette also uses Stim for Pauli sampling, the check mentioned above tests for circuit translation, noise insertion and scoring. Tasks involving non-Pauli noise such as leakage or coherent errors were evaluated with Plaquette’s other simulators, which are known to model these errors directly and more accurately than Stim.
Request access
Design your fault-tolerant architecture with Meridian.
Access for quantum hardware teams.
A member of our team will contact you when capacity becomes available.